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? 2007 microchip technology inc. ds22026b-page 1 mcp1725 features 500 ma output current capability input operating voltage range: 2.3v to 6.0v adjustable output voltage range: 0.8v to 5.0v standard fixed output voltages: - 0.8v, 1.2v, 1.8v, 2.5v, 3.0v, 3.3v, 5.0v other fixed output voltage options available upon request low dropout voltage: 210 mv typical at 500 ma typical output voltage tolerance: 0.5% stable with 1.0 f ceramic output capacitor fast response to load transients low supply current: 120 a (typical) low shutdown supply current: 0.1 a (typical) adjustable delay on power good output short circuit current limiting and overtemperature protection 2x3 dfn-8 and soic-8 package options applications high-speed driver chipset power networking backplane cards notebook computers network interface cards palmtop computers video graphics adapters 2.5v to 1.xv regulators description the mcp1725 is a 500 ma low dropout (ldo) linear regulator that provides high current and low output voltages in a very small package. the mcp1725 comes in a fixed (or adjustable) output voltage version, with an output voltage range of 0.8v to 5.0v. the 500 ma output current capability, combined with the low output voltage capability, make the mcp1725 a good choice for new sub-1.8v output voltage ldo applications that have high current demands. the mcp1725 is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. only 1 f of output capacitance is needed to stabilize the ldo. using cmos construction, the quiescent current consumed by the mcp1725 is typically less than 120 a over the entire input voltage range, making it attractive for portable computing applications that demand high output current. when shut down, the quiescent current is reduced to less than 0.1 a. the scaled-down output voltage is internally monitored and a power good (pwrgd) output is provided when the output is within 92% of regulation (typical). an external capacitor can be used on the c delay pin to adjust the delay from 200 s to 300 ms. the overtemperature and short circuit current-limiting provide additional protection for the ldo during system fault conditions. package types v in v in shdn gnd pwrgd c delay sense v out v in v in shdn gnd pwrgd c delay adj v out adjustable (soic-8) fixed (soic-8) v in v in shdn gnd pwrgd c delay sense v out 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 fixed (2x3 dfn) v in v in shdn gnd pwrgd c delay v out adjustable (2x3 dfn) adj 12 3 45 6 7 8 12 3 45 6 7 8 note: dfn tab is at ground potential. 500 ma, low voltage, low quie scent current ldo regulator downloaded from: http:///
mcp1725 ds22026b-page 2 ? 2007 microchip technology inc. typical application mcp1725 adjustable output voltage v in shdn gnd pwrgd c delay adj v out 12 3 45 6 7 8 1f pwrgd v out = 1.2v @ 500 ma 100 k 4.7 f v in = 2.3v to 2.8v on off v in 20 k 40 k r 1 r 2 c 1 c 2 r 3 1000 pf c 3 mcp1725 fixed output voltage v in shdn gnd pwrgd c delay sense v out 12 3 45 6 7 8 pwrgd v out = 1.8v @ 500 ma v in = 2.3v to 2.8v on off v in 1f 100 k 4.7 f c 1 c 2 r 1 1000 pf c 3 downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 3 mcp1725 functional block diagram - adjustable output ea + C v out pmos r f c f i sns overtemperature v ref comp 92% of v ref t delay pwrgd c delay v in driver w/limit and shdn gnd soft-start adj undervoltage lock out v in reference shdn shdn shdn sensing (uvlo) downloaded from: http:///
mcp1725 ds22026b-page 4 ? 2007 microchip technology inc. functional block diagram - fixed output ea + C v out pmos r f c f i sns overtemperature v ref comp 92% of v ref t delay pwrgd c delay v in driver w/limit and shdn gnd soft-start sense undervoltage lock out v in reference shdn shdn shdn sensing (uvlo) downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 5 mcp1725 1.0 electrical characteristics absolute maximum ratings ? v in ......................................................................... 6.5v maximum voltage on any pin ........................................(gnd C 0.3v) to (v in + 0.3)v maximum power dissipation..... ........ internally-limited ( note 6 ) output short circuit durati on ..................... continuous storage temperature .......................... -65c to +150c maximum junction temperature, t j ................ +150c esd protection on all pins (hbm/mm) .. 2kv; 200v ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any ot her conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ac/dc characteristics electrical specifications: unless otherwise noted, v in = v out(max) + v dropout(max) (note 1) , v r = 1.8v for adjustable output, i out = 1 ma, c in = c out = 4.7 f (x7r ceramic), t a = +25c. boldface type applies for junction temperatures, t j ( note 7 ) of -40c to +125c parameters sym min typ max units conditions input operating voltage v in 2.3 6.0 v note 1 input quiescent current i q 120 220 a i l = 0 ma, v in = note 1 , v out = 0.8v to 5.0v input quiescent current for shdn mode i shdn 0 . 1 3 a shdn = gnd maximum output current i out 500 m a v in = 2.3v to 6.0v v r = 0.8v to 5.0v, note 1 line regulation v out / (v out x v in ) 0.05 0.16 %/v (note 1) v in 6v load regulation v out /v out -1.0 0.5 1.0 %i out = 1 ma to 500 ma, ( note 4 ) output short circuit current i out_sc 1 . 2ar load <0.1 , peak current adjust pin characteristics (adjustable output only) adjust pin reference voltage v adj 0.402 0.410 0.418 vv in = 2.3v to v in =6.0v, i out = 1 ma adjust pin leakage current i adj -10 0.01 +10 na v in = 6.0v, v adj =0vto6v adjust temperature coefficient tcv out 40 ppm/c note 3 fixed-output characteristics (fixed output only) voltage regulation v out v r - 2.5% v r 0.5% v r + 2.5% v note 2 note 1: the minimum v in must meet two conditions: v in 2.3v and v in v out(max) + v dropout(max). 2: v r is the nominal regulator output voltage for the fixed cases. v r = 1.2v, 1.8v, etc. v r is the desired set point output voltage for the adjustable cases. v r = v adj * ((r 1 /r 2 )+1). figure 4-1 . 3: tcv out = (v out-high C v out-low ) *10 6 / (v r * temperature). v out-high is the highest voltage measured over the temperature range. v out-low is the lowest voltage measured over the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-cy cle pulse testing. load regulation is tested over a load range from 1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of v out = v r + v dropout(max) . 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., t a , t j , ja ). exceeding the maximum allowable power dissipation will cause the device operat ing junction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact device reliability. 7: the junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is small enough su ch that the rise in the junction temperature over the ambient temperature is not significant. downloaded from: http:///
mcp1725 ds22026b-page 6 ? 2007 microchip technology inc. dropout characteristics dropout voltage v in -v out 210 350 mv i out = 500 ma, (note 5) v in(min) =2.3v power good characteristics pwrgd input voltage operat- ing range v pwrgd_vin 1.0 6.0 v t a = +25c 1.2 6.0 t a = -40c to +125c for v in < 2.3v, i sink = 100 a pwrgd threshold voltage (referenced to v out ) v pwrgd_th % v out falling edge 89 92 95 v out < 2.5v fixed, v out = adj. 90 92 94 v out >= 2.5v fixed pwrgd threshold hysteresis v pwrgd_hys 1.0 2.0 3.0 %v out pwrgd output voltage low v pwrgd_l 0 . 2 0.4 vi pwrgd sink = 1.2 ma, adj = 0v, sense = 0v pwrgd leakage p wrgd _ lk 1n a v pwrgd = v in = 6.0v pwrgd time delay t pg rising edger pullup = 10 k i cdelay = 140 na (typ) 200 s c delay = open 10 30 55 ms c delay =0.01f 300 ms c delay =0.1f detect threshold to pwrgd active time delay t vdet-pwrgd 200 s v adj or v sense = v pwrgd_th + 20 mv to v pwrgd_th - 20 mv shutdown input logic high input v shdn-high 45 % v in v in = 2.3v to 6.0v logic low input v shdn-low 15 %v in v in = 2.3v to 6.0v shdn input leakage current shdn ilk -0.1 0.001 +0.1 a v in =6v, shdn =v in , shdn = gnd ac/dc characteristi cs (continued) electrical specifications: unless otherwise noted, v in = v out(max) + v dropout(max) (note 1) , v r = 1.8v for adjustable output, i out = 1 ma, c in = c out = 4.7 f (x7r ceramic), t a = +25c. boldface type applies for junction temperatures, t j ( note 7 ) of -40c to +125c parameters sym min typ max units conditions note 1: the minimum v in must meet two conditions: v in 2.3v and v in v out(max) + v dropout(max). 2: v r is the nominal regulator output voltage for the fixed cases. v r = 1.2v, 1.8v, etc. v r is the desired set point output voltage for the adjustable cases. v r = v adj * ((r 1 /r 2 )+1). figure 4-1 . 3: tcv out = (v out-high C v out-low ) *10 6 / (v r * temperature). v out-high is the highest voltage measured over the temperature range. v out-low is the lowest voltage measured over the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-cy cle pulse testing. load regulation is tested over a load range from 1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of v out = v r + v dropout(max) . 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., t a , t j , ja ). exceeding the maximum allowable power dissipation will cause the device operat ing junction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact device reliability. 7: the junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is small enough su ch that the rise in the junction temperature over the ambient temperature is not significant. downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 7 mcp1725 temperature specifications ac performance output delay from shdn t or 100 s shdn = gnd to v in v out = gnd to 95% v r output noise e n 2 . 0 v / hz i out = 200 ma, f = 1 khz, c out = 10 f (x7r ceramic), v out = 2.5v power supply ripple rejection ratio psrr 60 db f = 100 hz, c out = 10 f, i out = 10 ma, v inac = 30 mv pk-pk, c in = 0 f thermal shutdown temperature t sd 150 c i out = 100 a, v out = 1.8v, v in = 2.8v thermal shutdown hysteresis t sd 1 0 c i out = 100 a, v out = 1.8v, v in = 2.8v electrical specifications: unless otherwise indicated, all limits apply for v in = 2.3v to 6.0v. parameters sym min typ max units conditions temperature ranges operating junction temperature range t j -40 +125 c steady state maximum junction temperature t j +150 c transient storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8ld 2x3 dfn ja 76 c/w 4-layer jc51-7 standard board with vias jc 2 6 c / w thermal resistance, 8ld soic ja 163 c/w 4-layer jc51-7 standard board jc 38.8 c/w ac/dc characteristi cs (continued) electrical specifications: unless otherwise noted, v in = v out(max) + v dropout(max) (note 1) , v r = 1.8v for adjustable output, i out = 1 ma, c in = c out = 4.7 f (x7r ceramic), t a = +25c. boldface type applies for junction temperatures, t j ( note 7 ) of -40c to +125c parameters sym min typ max units conditions note 1: the minimum v in must meet two conditions: v in 2.3v and v in v out(max) + v dropout(max). 2: v r is the nominal regulator output voltage for the fixed cases. v r = 1.2v, 1.8v, etc. v r is the desired set point output voltage for the adjustable cases. v r = v adj * ((r 1 /r 2 )+1). figure 4-1 . 3: tcv out = (v out-high C v out-low ) *10 6 / (v r * temperature). v out-high is the highest voltage measured over the temperature range. v out-low is the lowest voltage measured over the temperature range. 4: load regulation is measured at a constant junction temperature using low duty-cy cle pulse testing. load regulation is tested over a load range from 1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of v out = v r + v dropout(max) . 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., t a , t j , ja ). exceeding the maximum allowable power dissipation will cause the device operat ing junction temperature to exceed the maximum +150c rating. sustained junction temperatures above +150c can impact device reliability. 7: the junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is small enough su ch that the rise in the junction temperature over the ambient temperature is not significant. downloaded from: http:///
mcp1725 ds22026b-page 8 ? 2007 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, v in = v out + 0.5v or v in = 2.3v (whichever is greater), i out = 1 ma, c in = c out = 4.7 f ceramic (x7r), shdn = v in , c delay = open, fixed output version, and t a = +25c. note: junction temperature (t j ) is approximated by soaking the device und er test to an ambient temperature equal to the desired junction temperature. the test time is small e nough such that the rise in j unction temperature over the ambient temperature is not significant. figure 2-1: quiescent current vs. input voltage (1.8v adjustable). figure 2-2: ground current vs. load current (1.2v adjustable). figure 2-3: quiescent current vs. junction temperature (1.8v adjustable). figure 2-4: line regulation vs. temperature (1.8v adjustable). figure 2-5: load regulation vs. temperature (adjustable version). figure 2-6: adjust pin voltage vs. temperature. note: the graphs and tables provided following this note are a st atistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics li sted herein are not tested or guaranteed. in some graphs or tables, the data presented may be outsi de the specified operating r ange (e.g., outside specified power supply range) and therefore outside the warranted range. 80 90 100 110 120 130 140 150 23456 input voltage (v) quiescent current (a) -45c 0c +25c +90c +130c i out = 0 ma 120 130 140 150 160 170 180 190 200 210 0 100 200 300 400 500 load current (ma) ground current (a) v in = 5.0v v in = 3.3v v in = 2.5v v out = 1.2v adj 80 90 100 110 120 130 140 150 -45 -20 5 30 55 80 105 130 temperature (c) quiescent current (a) v in = 5.0v v in = 2.3v v in = 3.3v v in = 6.0v i out = 0 ma 0.00 0.02 0.04 0.06 0.08 0.10 0.12 -45 -20 5 30 55 80 105 130 temperature (c) line regulation (%/v) i out = 1 ma i out = 50 ma i out = 250 ma i out = 100 ma i out = 500 ma v in = 2.3v to 6.0v 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 -45 -20 5 30 55 80 105 130 temperature (c) load regulation (%) v out = 5v v out = 3.3v v out = 1.8v v out = 0.8v i out = 1.0 ma to 500 ma 0.408 0.409 0.410 0.411 0.412 -45 -20 5 30 55 80 105 130 temperature (c) adjust pin voltage (v) v in = 5.0v v in = 6.0v v in = 2.3v, 3.0v, 4.0v i out = 1 ma downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 9 mcp1725 note: unless otherwise indicated, v in = v out + 0.5v or v in = 2.3v (whichever is greater), i out = 1 ma, c in = c out = 4.7 f ceramic (x7r), shdn = v in , c delay = open, fixed output version, and t a = +25c . figure 2-7: dropout voltage vs. load current (adjustable version). figure 2-8: dropout voltage vs. temperature (adjustable version). figure 2-9: power good (pwrgd) time delay vs. temperature (adjustable version). figure 2-10: quiescent current vs. input voltage (0.8v fixed). figure 2-11: quiescent current vs. input voltage (2.5v fixed). figure 2-12: ground current vs. load current. 0.00 0.05 0.10 0.15 0.20 0.25 0 100 200 300 400 500 load current (ma) dropout voltage (v) v out = 2.5v v out = 5.0v 0.16 0.18 0.20 0.22 0.24 0.26 0.28 -45 -20 5 30 55 80 105 130 temperature (c) dropout voltage (v) v out = 2.5v v out = 5.0v v out = 3.3v i out = 500 ma 25 26 27 28 29 30 31 32 33 34 35 -45 -20 5 30 55 80 105 130 temperature (c) power good time delay (ms) v in = 2.3v v in = 3.0v v in = 5.0v c delay = 0.01 f i out = 0 ma 80 90 100 110 120 130 140 150 23456 input voltage (v) quiescent current (a) -45c +130c +90c +25c 0c i out = 0 ma 90 100 110 120 130 140 150 3 3.5 4 4.5 5 5.5 6 input voltage (v) quiescent current (a) -45c 0c +25c +90c +135c i out = 0 ma 110 130 150 170 190 210 0 100 200 300 400 500 load current (ma) ground current (a) v out = 5.0v v out = 2.5v downloaded from: http:///
mcp1725 ds22026b-page 10 ? 2007 microchip technology inc. note: unless otherwise indicated, v in = v out + 0.5v or v in = 2.3v (whichever is greater), i out = 1 ma, c in = c out = 4.7 f ceramic (x7r), shdn = v in , c delay = open, fixed output version, and t a = +25c . figure 2-13: quiescent current vs. junction temperature. figure 2-14: i shdn vs. temperature. figure 2-15: line regulation vs. temperature (0.8v fixed). figure 2-16: line regulation vs. temperature (2.5v fixed). figure 2-17: load regulation vs. temperature (v out < 2.5v fixed). figure 2-18: load regulation vs. temperature (v out 2.5v fixed). 80 90 100 110 120 130 140 -45 -20 5 30 55 80 105 130 junction temperature (c) quiescent current (a) v out = 0.8v v out = 2.5v i out = 0 ma 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -45 -20 5 30 55 80 105 130 temperature (c) i shdn (a) v in = 2.3v v in = 6.0v v in = 3.3v v out = 0.8v 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 -45 -20 5 30 55 80 105 130 temperature (c) line regulation (%/v) i out = 1 ma i out = 500 ma i out = 250 ma i out = 100 ma i out = 50 ma v in = 2.3v to 6.0 v v out = 0.8 v 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 -45 -20 5 30 55 80 105 130 temperature (c) line regulation (%/v) i out = 1 ma i out = 250 ma i out = 500 ma i out = 100 ma i out = 50 ma v out = 2.5 v v in = 3.0v to 6.0 v 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 -45 -20 5 30 55 80 105 130 temperature (c) load regulation (%) v out = 1.2v i out = 1.0 ma to 500 ma v out = 0.8v -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -45 -20 5 30 55 80 105 130 temperature (c) load regulation (%) v out = 2.5v v out = 5.0v i out = 1.0 ma to 500 ma downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 11 mcp1725 note: unless otherwise indicated, v in = v out + 0.5v or v in = 2.3v (whichever is greater), i out = 1 ma, c in = c out = 4.7 f ceramic (x7r), shdn = v in , c delay = open, fixed output version, and t a = +25c . figure 2-19: dropout voltage vs. load current. figure 2-20: dropout voltage vs. temperature. figure 2-21: short circuit current vs. input voltage. figure 2-22: output noise voltage density vs. frequency. figure 2-23: power supply ripple rejection (psrr) vs. frequency (v out = 1.2v adj.). figure 2-24: power supply ripple rejection (psrr) vs. frequency (v out = 1.2v adj.). 0.00 0.05 0.10 0.15 0.20 0.25 0 100 200 300 400 500 load current (ma) dropout voltage (v) v out = 5.0v v out = 2.5v 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 -45 -20 5 30 55 80 105 130 temperature (c) dropout voltage (v) v out = 5.0v v out = 2.5v i load = 500 ma 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 3.03.54.04.55.05.56.0 input voltage (v) short circuit current (a) i steady state i peak v out = 2.5v fixed c in = 3000 f 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 frequency (khz) noise (v/ hz) v in = 3.3v v out = 2.5v v in = 2.3v v out = 0.8v i load = 200 ma c out = 1 f c in = 10 f -80 -70 -60 -50 -40 -30 -20 -10 0 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) v r =1.2v adj c out =4.7 f ceramic x7r v in =2.5v c in =0 f i out =10 ma -80 -70 -60 -50 -40 -30 -20 -10 0 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) v r =1.2v adj c out =22 f ceramic x7r v in =2.5v c in =0 f i out =10 ma downloaded from: http:///
mcp1725 ds22026b-page 12 ? 2007 microchip technology inc. note: unless otherwise indicated, v in = v out + 0.5v or v in = 2.3v (whichever is greater), i out = 1 ma, c in = c out = 4.7 f ceramic (x7r), shdn = v in , c delay = open, fixed output version, and t a = +25c. figure 2-25: power supply ripple rejection (psrr) vs. frequency (v out = 2.5v fixed). figure 2-26: power supply ripple rejection (psrr) vs. frequency (v out = 2.5v fixed). figure 2-27: 2.5v (adj.) startup from v in . figure 2-28: 2.5v (adj.) startup from shutdown. figure 2-29: power good (pwrgd) timing with cdelay of 1000 pf (2.5v fixed). figure 2-30: power good (pwrgd) timing with c delay of 0.01 f (2.5v fixed). -80 -70 -60 -50 -40 -30 -20 -10 0 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) v r =2.5v fixed c out =4.7 f ceramic x7r v in =3.3v c in =0 f i out =10 ma -80 -70 -60 -50 -40 -30 -20 -10 0 0.01 0.1 1 10 100 1000 frequency (khz) psrr (db) v r =2.5v fixed c out =22 f ceramic x7r v in =3.3v c in =0 f i out =10 ma downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 13 mcp1725 note: unless otherwise indicated, v in = v out + 0.5v or v in = 2.3v (whichever is greater), i out = 1 ma, c in = c out = 4.7 f ceramic (x7r), shdn = v in , c delay = open, fixed output version, and t a = +25c . figure 2-31: dynamic line response (5.0v fixed). figure 2-32: dynamic line response (2.5v fixed). figure 2-33: dynamic load response (2.5v fixed, 1 ma to 500 ma). figure 2-34: dynamic load response (2.5v fixed, 10 ma to 500 ma). downloaded from: http:///
mcp1725 ds22026b-page 14 ? 2007 microchip technology inc. 3.0 pin description the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 input voltage supply (v in ) connect the unregulated or regulated input voltage source to v in . if the input voltage source is located several inches away from the ldo, or the input source is a battery, it is recommended that an input capacitor be used. a typical input capacitance value of 1 f to 10 f should be sufficient for most applications. 3.2 shutdown control input (shdn ) the shdn input is used to turn the ldo output voltage on and off. when the shdn input is at a logic-high level, the ldo output voltage is enabled. when the shdn input is pulled to a logic-low level, the ldo output voltage is disabled. when the shdn input is pulled low, the pwrgd output also goes low and the ldo enters a low quiescent current shutdown state where the typical quiescent current is 0.1 a. 3.3 ground (gnd) connect the gnd pin of the ldo to a quiet circuit ground. this will help the ldo power supply rejection ratio and noise performance. the ground pin of the ldo only conducts the quiescent current of the ldo (typically 120 a), so a heavy trace is not required. for applications that have s witching or noisy inputs, tie the gnd pin to the return of the output capacitor. ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 3.4 power good output (pwrgd) the pwrgd output is an open-drain output used to indicate when the ldo output voltage is within 92% (typically) of its nominal regulation value. the pwrgd threshold has a typical hysteresis value of 2%. the pwrgd output is typically delayed by 200 s (typical, no capacitance on c delay pin) from the time the ldo output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. this delay time is controlled by the c delay pin. 3.5 power good delay set-point input (c delay ) the c delay input sets the power-up delay time for the pwrgd output. by connecting an external capacitor from the c delay pin to ground, the typical delay times for the pwrgd output can be adjusted from 200 s (no capacitance) to 300 ms (0.1 f capacitor). this allows for the optimal setting of the system reset time. fixed output adjustable output name description 11v in input voltage supply 22v in input voltage supply 3 3 shdn shutdown control input (active-low) 4 4 gnd ground 5 5 pwrgd power good output (open-drain) 66c delay power good delay set-point input 7 adj voltage sense input (adjustable version) 7 sense voltage sense input (fixed voltage version) 88v out regulated output voltage exposed pad exposed pad ep exposed pad of the dfn package (ground potential) downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 15 mcp1725 3.6 output voltage sense/adjust input (adj/sense) 3.6.1 adj for adjustable applications, the output voltage is connected to the adj input through a resistor divider that sets the output voltage regulation value. this provides the user the ca pability to set the output voltage to any value they de sire within the 0.8v to 5.0v range of the device. 3.6.2 sense for fixed output voltage versions of the device, the sense input is used to provide output voltage feedback to the internal circ uitry of the mcp1725. the sense pin typically improves load regulation by allowing the device to compensate for voltage drops due to packaging and circuit board layout. 3.7 regulated output voltage (v out ) the v out pin(s) is the regulated output voltage of the ldo. a minimum output capacitance of 1.0 f is required for ldo stability. the mcp1725 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. see section 4.3 output capacitor for output capacitor se lection guidance. 3.8 exposed pad (ep) the 2x3 dfn package has an exposed pad on the bottom of the package. this pad should be soldered to the printed circuit board (pcb) to aid in the removal of heat from the package during operation. the exposed pad is at the ground potential of the ldo. downloaded from: http:///
mcp1725 ds22026b-page 16 ? 2007 microchip technology inc. 4.0 device overview the mcp1725 is a high output current, low dropout (ldo) voltage regulator with an adjustable delay power-good output and shutdown control input. the low dropout voltage of 210 mv typical at 0.5a of current makes it ideal for battery-powered applications. unlike other high output current ldos, the mcp1725 only draws a maximum of 220 a of quiescent current. 4.1 ldo output voltage the mcp1725 ldo is available with either a fixed output voltage or an adjustable output voltage. the output voltage range is 0.8v to 5.0v for both versions. 4.1.1 adjust input the adjustable version of the mcp1725 uses the adj pin (pin 7) to get the output voltage feedback for output voltage regulation. this allows the user to set the output voltage of the device with two external resistors. the nominal voltage for adj is 0.41v. figure 4-1 shows the adjustable version of the mcp1725. resistors r 1 and r 2 form the resistor divider network necessary to set the output voltage. with this configuration, the equation for setting v out is: equation 4-1: figure 4-1: typical adjustable output voltage application circuit. the allowable resistance value range for resistor r 2 is from 10 k to 200 k . solving the equation for r 1 yields the following equation: equation 4-2: 4.2 output current and current limiting the mcp1725 ldo is tested and ensured to supply a minimum of 0.5a of output current. the mcp1725 has no minimum output load, so the output load current can go to 0 ma and the ldo will continue to regulate the output voltage to within tolerance. the mcp1725 also incorporat es an output current limit. if the output voltage falls below 0.7v due to an overload condition (usually represents a shorted load condition), the output current is limited to 1.2a (typical). if the over- load condition is a soft overload, the mcp1725 will supply higher load currents of up to 1a. the mcp1725 should not be operated in th is condition continuously as it may result in failure of the device. however, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 0.5a or less. output overload conditions may also result in an over- temperature shutdown of the device. if the junction temperature rises above 150c, the ldo will shut down the output voltage. see section 4.9 overtem- perature protection for more information on overtemperature shutdown. 4.3 output capacitor the mcp1725 requires a minimum output capacitance of 1 f for output voltage stability. ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. aluminum-electrolytic and tantalum capacitors can be used on the ldo output as well. the equivalent series resistance (esr) of the el ectrolytic output capacitor must be no greater than 1 ohm. the output capacitor should be located as clos e to the ldo output as is practical. ceramic materials x7r and x5r have low temperature coefficients and are well within the acceptable esr range required. a typical 1 f x7r 0805 capacitor has an esr of 50 milli-ohms. larger ldo output capacitors can be used with the mcp1725 to improve dynamic performance and power supply ripple rejection performance. a maximum of 22 f is recommended. aluminum-electrolytic capacitors are not recommended for low-temperature applications of < -25c. v out v adj r 1 r 2 + r 2 ------------------ ?? ?? = where: v out = ldo output voltage v adj =adj pin voltage (typically 0.41v) v in shdn gnd pwrgd c delay adj v out 12 3 45 6 7 8 1f v out 4.7 f v in on off v in r 1 r 2 c 1 c2 1000 pf c 3 mcp1725-adj r 1 r 2 v out v adj C v adj -------------------------------- ?? ?? = where: v out = ldo output voltage v adj =adj pin voltage (typically 0.41v) downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 17 mcp1725 4.4 input capacitor low input source impedance is necessary for the ldo output to operate proper ly. when operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the ldo, some input capacitance is recommended. a minimum of 1.0 f to 4.7 f is recommended for most applications. for applications that have output step load requirements, the input capa citance of the ldo is very important. the input capacitance provides the ldo with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. for good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. the capacitor should be placed as close to the input of the ldo as is practical. larger input capacitors will also help reduce any high-frequency noise on the input and output of the ldo and redu ce the effects of any inductance that exists between the input source voltage and the input capacitance of the ldo. 4.5 power good output (pwrgd) the pwrgd output is used to indicate when the output voltage of the ldo is within 92% (typical value, see section 1.0 electri cal characteristics for minimum and maximum specifications) of its nominal regulation value. as the output voltage of the ldo rises, the pwrgd output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. once this threshold has been exceeded, the power good time delay is started (shown as t pg in section 1.0 electri cal characteristics ). the power good time delay is adjustable via the c delay pin of the ldo (see section 4.6 c delay input ). by placing a capacitor from the c delay pin to ground, the power good time delay can be adjusted from 200 s (no capacitance) to 300 ms (0.1 f capacitor). after the time delay period, the pwrgd output will go high, indi- cating that the output voltage is stable and within regulation limits. if the output voltage of the ldo falls below the power good threshold, the power good output will transition low. the power good circuitry has a 170 s delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. see figure 4-2 for power good timing characteristics. when the ldo is put into shutdown mode using the shdn input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. the timing diagram for the power good output when using the shutdown input is shown in figure 4-3 . the power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the ldo input voltage. this output is capable of sinking 1.2 ma (v pwrgd < 0.4v maximum). figure 4-2: power good timing. figure 4-3: power good timing from shutdown. t pg t vdet_pwrgd v pwrgd_th v out pwrgd v ol v oh v in shdn v out 30 s 70 s t or pwrgd t pg downloaded from: http:///
mcp1725 ds22026b-page 18 ? 2007 microchip technology inc. 4.6 c delay input the c delay input is used to provide the power-up delay timing for the power good output, as discussed in the previous section. by adding a capacitor from the c delay pin to ground, the pwrgd power-up time delay can be adjusted from 200 s (no capacitance on c delay ) to 300 ms (0.1 f of capacitance on c delay ). see section 1.0 electri cal characteristics for c delay timing tolerances. once the power good threshold (rising) has been reached, the c delay pin charges the external capacitor to v in . the charging current is 140 na (typical). the pwrgd output will transition high when the c delay pin voltage has charged to 0.42v. if the output falls below the power good threshold limit during the charging time between 0.0v and 0.42v on the c delay pin, the c delay pin voltage will be pulled to ground, thus reset- ting the timer. the c delay pin will be held low until the output voltage of the ldo has once again risen above the power good rising threshold. a timing diagram showing c delay , pwrgd and v out is shown in figure 4-4 . figure 4-4: c delay and pwrgd timing diagram. 4.7 shutdown input (shdn ) the shdn input is an active-low input signal that turns the ldo on and off. the shdn threshold is a percentage of the input voltage. the typical value of this shutdown threshold is 30% of v in , with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. the shdn input will ignore low-going pulses (pulses meant to shut down the ldo) that are up to 400 ns in pulse width. if the shutdown input is pulled low for more than 400 ns, the ldo will enter shutdown mode. this small bit of filtering helps to reject any system noise spikes on the shutdown input signal. on the rising edge of the shdn input, the shutdown circuitry has a 30 s delay before allowing the ldo output to turn on. this delay helps to reject any false turn-on signals or noise on the shdn input signal. after the 30 s delay, the ldo output enters its soft-start period as it rises from 0v to its final regulation value. if the shdn input signal is pulled low during the 30 s delay period, the timer will be reset and the delay time will start over again on the next rising edge of the shdn input. the total time from the shdn input going high (turn-on) to the ldo output being in regulation is typically 100 s. see figure 4-5 for a timing diagram of the shdn input. figure 4-5: shutdown input timing diagram. v out t pg v pwrgd_th c delay c delay threshold (0.42v) pwrgd 0v v in (typ) shdn v out 30 s 70 s t or 400 ns (typ) downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 19 mcp1725 4.8 dropout voltage and undervoltage lockout dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a v r + 0.6v differential applied. the mcp1725 ldo has a very low dropout voltage specification of 210 mv (typical) at 0.5a of output current. see section 1.0 electrical characteristics for maximum dropout voltage specifications. the mcp1725 ldo operates across an input voltage range of 2.3v to 6.0v and incorporates input undervolt- age lockout (uvlo) circuitry that keeps the ldo output voltage off until the input voltage reaches a minimum of 2.18v (typical) on the rising edge of the input voltage. as the input voltage falls, the ldo output will remain on until the input voltage level reaches 2.04v (typical). since the mcp1725 ldo undervoltage lockout activates at 2.04v as the input voltage is falling, the dropout voltage specificat ion does not apply for output voltages that are less than 1.9v. for high-current applications, voltage drops across the pcb traces must be taken into account. the trace resistances can cause significant voltage drops between the input voltage source and the ldo. for applications with input voltages near 2.3v, these pcb trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. 4.9 overtemperature protection the mcp1725 ldo has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150 c. if the ldo junction temperature does reach 150 c, the ldo output will be turned off until the junction temperature cools to approximately 140 c, at which point the ldo output will automatically resume normal operation. if the internal power dissipation continues to be excessive, the device will again shut off. the junction temperature of the die is a function of power dissipatio n, ambient temperature and package thermal resistance. see section 5.0 appli- cation circuits/issues for more information on ldo power dissipation and junction temperature. downloaded from: http:///
mcp1725 ds22026b-page 20 ? 2007 microchip technology inc. 5.0 application circuits/ issues 5.1 typical application the mcp1725 is used for applic ations that require high ldo output current and a power good output. figure 5-1: typical application circuit. 5.1.1 application conditions 5.2 power calculations 5.2.1 power dissipation the internal power dissipation within the mcp1725 is a function of input voltage, out put voltage, output current, and quiescent current. equation 5-1 can be used to calculate the internal power dissipation for the ldo. equation 5-1: in addition to the ldo pass element power dissipation, there is power dissipation within the mcp1725 as a result of quiescent or ground current. the power dissipation as a result of the ground current can be calculated using the following equation: equation 5-2: the total power dissipated within the mcp1725 is the sum of the power dissipated in the ldo pass device and the p(i gnd ) term. because of the cmos construction, the typical i gnd for the mcp1725 is 120 a. operating at 3.465v results in a power dissipa- tion of 0.42 milli-watts. for most applications, this is small compared to the ldo pass device power dissipation and can be neglected. the maximum continuous operating junction temperature specified for the mcp1725 is +125 c . to estimate the internal junction temperature of the mcp1725, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (r ja ) of the device. the thermal resistance from junction to ambient for the 2x3 dfn package is estimated at 76 c/w. equation 5-3: package type = 2x3 dfn8 input voltage range = 3.3v 5% v in maximum = 3.465v v in minimum = 3.135v v dropout (max) = 0.350v v out (typical) = 2.5v i out = 0.5a maximum p diss (typical) = 0.4w temperature rise = 30.4 c v in shdn gnd pwrgd c delay sense v out 12 3 4 5 6 7 8 10 f v out = 2.5v @ 0.5a 10 f v in = 3.3v on off v in r 1 c 1 c 2 1000 pf c 3 mcp1725-2.5 10k pwrgd p ldo v in max ) () v out min () C () i out max ) () = where: p ldo = ldo pass device internal power dissipation v in(max) = maximum input voltage v out(min) = ldo minimum output voltage p ignd () v in max () i vin = where: p i(gnd = power dissipation due to the quiescent current of the ldo v in(max) = maximum input voltage i vin = current flowing in the v in pin with no ldo output current (ldo quiescent current) t jmax () p total r ja t amax + = t j(max) = maximum continuous junction temperature p total = total device power dissipation r ja = thermal resistance from junction to ambient t amax = maximum ambient temperature downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 21 mcp1725 the maximum power dissipa tion capability for a package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient temperature for the application. equation 5-4 can be used to determine the package maximum internal power dissipation. equation 5-4: equation 5-5: equation 5-6: 5.3 typical application internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation is calculated in the following example. the power dissi- pation as a result of ground current is small enough to be neglected. example 5-1: power dissipation example 5.3.1 device junction temperature rise the internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. the thermal resistance from junction-to-ambient (r ja ) is derived from an eia/jedec standard for measuring thermal resistance for small surface-mount packages. the eia/jedec specification is jesd51-7 high effective thermal conductivity test board for leaded surface-mount packages . the standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. the actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. refer to an792, a method to determine how much power a sot23 can dissipate in an appli- cation (ds00792), for more information regarding this subject. p dmax () t jmax () t amax () C () r ja --------------------------------------------------- = p d(max) = maximum device power dissipation t j(max) = maximum continuous junction temperature t a(max) = maximum ambient temperature r ja = thermal resistance from junction to ambient t jrise () p dmax () r ja = t j(rise) = rise in device junction temperature over the ambient temperature p d(max) = maximum device power dissipation r ja = thermal resistance from junction to ambient t j t jrise () t a + = t j = junction temperature t j(rise) = rise in device junction temperature over the ambient temperature t a = ambient temperature package package type = 2x3 dfn input voltage v in =3.3v 5% ldo output voltage and current v out =2.5v i out =0.5a maximum ambient temperature t a(max) = 60c internal power dissipation p ldo(max) =(v in(max) C v out(min) ) x i out(max) p ldo = ((3.3v x 1.05) C (2.5v x 0.975)) x 0.5a p ldo = 0.51 watts t j(rise) =p total x r ja t jrise = 0.51 w x 76.0 c/w t jrise =38.8 c downloaded from: http:///
mcp1725 ds22026b-page 22 ? 2007 microchip technology inc. 5.3.2 junction temperature estimate to estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. for this example, the worst-case junction temperature is estimated below: as you can see from the result, this application will be operating near around a junction temperature of 100c. the pcb layout for this application is very important as it has a signific ant impact on the junction- to-ambient thermal resistance (r ja ) of the 2x3 dfn package, which is very important in this application. 5.3.3 maximum package power dissipation at 60c ambient temperature from this table, you can see the difference in maximum allowable power dissipation between the 2x3 dfn package and the 8-pin soic package. this difference is due to the exposed meta l tab on the bottom of the dfn package. the exposed tab of the dfn package provides a very good thermal path from the die of the ldo to the pcb. the pcb then acts like a heatsink, providing more area to dist ribute the heat generated by the ldo. 5.4 c delay calculations (typical) t j =t jrise + t a(max) t j = 38.8c + 60.0c t j = 98.8c 2x3 dfn (76c/w r ja ): p d(max) = (125c C 60c) / 76c/w p d(max) = 0.855w soic8 (163c/watt r ja ): p d(max) = (125c C 60c)/ 163c/w p d(max) = 0.399w ci t v ------- ? = where: c=c delay capacitor i=c delay charging current, 140 na typical. t = time delay v=c delay threshold voltage, 0.42v typical ci t v ------- ? 140na t ? () 0.42v --------------------------------- - 333.3 09 C 10 t ? == = for a delay of 300ms, c = 333.3e-09 *.300 c = 100e-09 f (0.1 f) downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 23 mcp1725 6.0 packaging information 6.1 package marking information 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn 250802e sn^^0750 256 8-lead dfn (2x3) example: 3 e abl 750 25 xxx yww nn standard extended temp code voltage options * code voltage options * abl 0.8 abr 3.0 abm 1.2 abs 3.3 abp 1.8 abt 5.0 abq 2.5 abu adj * custom output voltages available upon request. contact your local microchip sales office for more information. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e downloaded from: http:///
mcp1725 ds22026b-page 24 ? 2007 microchip technology inc.

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mcp1725 ds22026b-page 26 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 27 mcp1725 appendix a: revision history revision b (december 2007) updated temperature specifications in section 1.0 electri cal characteristics . updated section 6.0 packaging information . updated templates. revision a (december 2006) original release of this document. downloaded from: http:///
mcp1725 ds22026b-page 28 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 29 mcp1725 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp1725: 500 ma low dropout regulator mcp1725t: 500 ma low dropout regulator tape and reel output voltage *: 08 = 0.8v standard 12 = 1.2v standard 18 = 1.8v standard 25 = 2.5v standard 30 = 3.0v standard 33 = 3.3v standard 50 = 5.0v standard *contact factory for other output voltage options extra feature code: 0 = fixed tolerance: 2 = 2.0% (standard) temperature: e = -40 c to +125 c package type: mc = plastic dual flat no lead (dfn) (2x3 body), 8-lead sn = plastic small outline (150 mil body), 8-lead part no. x xx output feature code device voltage x tolerance x/ temp. xx package examples: a) mcp1725-0802e/mc: 0.8v low dropout regulator, 8ld dfn pkg. b) mcp1725t-1202e/mc: tape and reel, 1.2v low dropout regulator, 8ld dfn pkg. c) mcp1725-1802e/mc: 1.8v low dropout voltage regulator, 8ld dfn pkg. d) mcp1725t-2502e/mc: tape and reel, 2.5v low dropout voltage regulator, 8ld dfn pkg. e) mcp1725-3002e/mc: 3.0v low dropout voltage regulator, 8ld dfn pkg. f) mcp1725-3302e/mc: 3.3v low dropout voltage regulator, 8ld dfn pkg. g) mcp1725t-5002e/mc: tape and reel, 5.0v low dropout voltage regulator, 8ld dfn pkg. h) mcp1725-adje/mc: adj low dropout voltage regulator, 8ld dfn pkg. i) mcp1725t-0802e/sn: tape and reel, 0.8v low dropout voltage regulator, 8ld soic pkg. j) mcp1725-1202e/sn: 1.2v low dropout voltage regulator, 8ld soic pkg. k) mcp1725t-1802e/sn: tape and reel, 1.8v low dropout voltage regulator, 8ld soic pkg. l) mcp1725-2502e/sn: 2.5v low dropout voltage regulator, 8ld soic pkg. m) mcp1725-3002e/sn: 3.0v low dropout voltage regulator, 8ld soic pkg. n) mcp1725-3302e/sn: 3.3v low dropout voltage regulator, 8ld soic pkg. o) mcp1725t-5002e/sn: tape and reel, 5.0v low dropout voltage regulator, 8ld soic pkg. p) mcp1725t-adje/sn: tape and reel, adj low dropout voltage regulator, 8ld soic pkg. downloaded from: http:///
mcp1725 ds22026b-page 30 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds22026b-page 31 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip te chnology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
ds22026b-page 32 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 10/05/07 downloaded from: http:///

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